Satzoda,2010 “A low error and high performance multiplexer-based truncated multiplier

Abstract—This paper proposes a novel adaptive pseudo-carry compen-sation truncation (PCT) scheme, which is derived for the multiplexer based array multiplier. The proposed method yields low average error among ex-isting truncation methods. The new PCT based truncated array multiplier outperforms other existing truncated array multipliers by as much as 25% in terms of silicon area and delay, and consumes about 40 % less dynamic power than the full-width multiplier for 32-bit operation. The proposed truncation scheme is applied to an image compression algorithm. Due to its low truncation error, the mean square errors (MSE) of various recon-structed images are found to be comparable to those obtained with full-pre-cision multiplication. Index Terms—Computer arithmetic, digital multiplier, truncated multi-plier, truncation scheme, VLSI design. I